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PE43072 参数 Datasheet PDF下载

PE43072图片预览
型号: PE43072
PDF下载: 下载PDF文件 查看货源
内容描述: 50 Ω RF数字衰减器7位, 31.75分贝, DC- 4.0 GHz的 [50 Ω RF Digital Attenuator 7-bit, 31.75 dB, DC-4.0 GHz]
分类和应用: 衰减器
文件页数/大小: 11 页 / 465 K
品牌: PSEMI [ Peregrine Semiconductor ]
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PE43702  
Product Specification  
Figure 17. Evaluation Board Layout  
Peregrine Specification 101-0310  
Evaluation Kit  
The Digital Attenuator Evaluation Kit board was  
designed to ease customer evaluation of the  
PE43702 Digital Step Attenuator.  
Direct-Parallel Programming Procedure  
For automated direct-parallel programming,  
connect the test harness provided with the EVK  
from the parallel port of the PC to the J1 & Serial  
header pin and set the D0-D6 SP3T switches to  
the ‘MIDDLE’ toggle position. Position the  
Parallel/Serial (P/S) select switch to the Parallel  
(or left) position. The evaluation software is  
written to operate the DSA in either Parallel or  
Serial-Addressable Mode. Ensure that the  
software is set to program in Direct-Parallel mode.  
Using the software, enable or disable each setting  
to the desired attenuation state. The software  
automatically programs the DSA each time an  
attenuation state is enabled or disabled.  
For manual direct-parallel programming,  
disconnect the test harness provided with the EVK  
from the J1 and Serial header pins. Position the  
Parallel/Serial (P/S) select switch to the Parallel  
(or left) position. The LE pin on the Serial header  
must be tied to VDD. Switches D0-D6 are SP3T  
switches which enable the user to manually  
program the parallel bits. When any input D0-D6  
is toggled ‘UP’, logic high is presented to the  
parallel input. When toggled ‘DOWN’, logic low is  
presented to the parallel input. Setting D0-D6 to  
the ‘MIDDLE’ toggle position presents an OPEN,  
which forces an on-chip logic low. Table 9 depicts  
the parallel programming truth table and Fig. 16  
illustrates the parallel programming timing  
diagram.  
Note: Reference Figure 18 for Evaluation Board Schematic  
as the parallel bits are applied. The user must  
then pulse LE from 0V to VDD and back to 0V to  
latch the programming word into the DSA. LE  
must be logic low prior to programming the next  
word.  
Serial Programming Procedure  
Position the Parallel/Serial (P/S) select switch to  
the Serial (or right) position. The evaluation  
software is written to operate the DSA in either  
Parallel or Serial Mode. Ensure that the software  
is set to program in Serial mode. Using the  
software, enable or disable each setting to the  
desired attenuation state. The software  
automatically programs the DSA each time an  
attenuation state is enabled or disabled.  
Latched-Parallel Programming Procedure  
For automated latched-parallel programming, the  
procedure is identical to the direct-parallel  
method. The user only must ensure that Latched-  
Parallel is selected in the software.  
For manual latched-parallel programming, the  
procedure is identical to direct-parallel except now  
the LE pin on the Serial header must be logic low  
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.  
Document No. 70-0244-03 UltraCMOS™ RFIC Solutions  
Page 8 of 11