PE9601
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
Pin Name
S_WR
13
D
4
M
4
Sdata
14
D
5
M
5
Sclk
15
D
6
M
6
FSELS
16
D
7
Pre_en
17
GND
FSELP
18
A
0
Direct
Serial
E_WR
19
A
1
M2_WR
20
A
2
Smode
21
A
3
22
23
24
25
26
27
28
29
Bmode
V
DD
M1_WR
A_WR
Hop_WR
F
in
F
in
GND
Direct
ALL
ALL
Parallel
Parallel
Serial, Parallel
ALL
ALL
ALL
Input
Input
(Note 1)
Input
Input
Input
Input
Input
Direct
Serial, Parallel
Input
Input
Parallel
Direct
Parallel
Input
Input
Input
Input
Input
Parallel
Direct
Serial
Parallel
Direct
Serial
Parallel
Direct
Serial
Parallel
Direct
ALL
Parallel
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Interface Mode
Serial
Type
Input
Description
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked.
Primary register data are transferred to the secondary register on S_WR or
Hop_WR rising edge.
Parallel data bus bit4
M Counter bit4
Binary serial data input. Input data entered MSB first.
Parallel data bus bit5.
M Counter bit5.
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR
“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
Parallel data bus bit6.
M Counter bit6.
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0)
for programming of internal counters while in Serial Interface Mode.
Parallel data bus bit7 (MSB).
Prescaler enable, active “low”. When “high”, F
in
bypasses the prescaler.
Ground.
Selects contents of primary register (FSELP=1) or secondary register (FSELP=0)
for programming of internal counters while in Parallel Interface Mode.
A Counter bit0 (LSB).
Enhancement register write enable. While E_WR is “high”, Sdata can be serially
clocked into the enhancement register on the rising edge of Sclk.
Enhancement register write. D[7:0] are latched into the enhancement register on
the rising edge of E_WR.
A Counter bit1.
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising
edge of M2_WR.
A Counter bit2.
Selects serial bus interface mode (Bmode=0,
Smode=1) or Parallel Interface Mode
(Bmode=0, Smode=0).
A Counter bit3 (MSB).
Selects direct interface mode (Bmode=1).
Same as pin 1.
M1 write. D[7:0] are latched into the primary register (Pre_en,
M[6:0]) on the rising
edge of M1_WR.
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising
edge of A_WR.
Hop write. The contents of the primary register are latched into the secondary
register on the rising edge of Hop_WR.
Prescaler input from the VCO. Input voltage = 223 mV RMS for guaranteed
operation.
Prescaler complementary input. A bypass capacitor should be placed as close as
possible to this pin and be connected directly to the ground plane.
Ground.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 14
Document No. 70-0025-05
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