PE9704
Advance Information
Register Programming
Serial Interface Mode
Serial Interface Mode is selected by setting the
D
MODE
input “low”.
While the E_WR input is “low”, serial data (DATA
input), B
0
to B
19
, is clocked into a buffer register on
the rising edge of CLOCK, LSB (B
0
) first. The
contents from this buffer register are transferred into
the frequency control register on the rising edge of
S_WR according to the timing diagram shown in
Figure 3. This data controls the counters as shown
in Table 7.
While the E_WR input is “high”, serial data (DATA
input), B
0
to B
7
, is clocked into a buffer register on
the rising edge of CLOCK, LSB (B
0
) first. The
contents from this buffer register are transferred into
the enhancement register on the falling edge of
E_WR according to the timing diagram shown in
Figure 3. After the falling edge of E_WR, the data
provides control bits as shown in Table 8. These
bits are active when the
Enh
input is “low”.
Direct Interface Mode
Direct Interface Mode is selected by setting the
D
MODE
input “high”. In this mode, the counter values
are set directly at external pins as shown in Table 7
and Figure 2. All frequency control register bits are
addressable except PB (it is not possible to bypass
the ÷10/11 dual modulus prescaler in Direct Mode).
Table 7. Frequency Register Programming
Interface
Mode
Serial*
Direct
Enh
1
1
D
MODE
0
1
R
5
B
0
R
5
R
4
B
1
R
4
M
8
B
2
M
8
M
7
B
3
M
7
PB
B
4
0
M
6
B
5
M
6
M
5
B
6
M
5
M
4
B
7
M
4
M
3
B
8
M
3
M
2
B
9
M
2
M
1
B
10
M
1
M
0
B
11
M
0
R
3
B
12
R
3
R
2
B
13
R
2
R
1
B
14
R
1
R
0
B
15
R
0
A
3
B
16
A
3
A
2
B
17
A
2
A
1
B
18
A
1
A
0
B
19
A
0
* Data is clocked serially on CLOCK rising edge while E_WR is “low” and transferred to frequency register on S_WR rising edge.
LSB (first in)
MSB (last in)
Table 8. Enhancement Register Programming
Interface
Mode
Serial**
Enh
0
D
MODE
X
Reserved*
B
0
Reserved*
B
1
fp output
B
2
Power
down
B
3
Counter
load
B
4
MSEL
output
B
5
fc output
B
6
Reserved*
B
7
* Program to 0
* Data is clocked serially on CLOCK rising edge while E_WR is “low” and transferred to frequency register on S_WR rising edge.
LSB (first in)
MSB (last in)
Copyright
Peregrine Semiconductor Corp. 2003
File No. 70/0083~00B
| |
UTSi
CMOS RFIC SOLUTIONS
Page 8 of 12
PEREGRINE [ PEREGRINE SEMICONDUCTOR CORP. ]
