PE9704
Advance Information
Figure 3. Serial Interface Mode Timing Diagram
DATA
E_WR
t
EC
t
CE
CLOCK
S_WR
t
DSU
t
DHLD
t
ClkH
t
ClkL
t
CWR
t
PW
t
WRC
Enhancement Register
The functions of the enhancement register bits are shown below. All bits are active high. Operation is
undefined if more than one output is sent to
D
OUT
.
Table 9. Enhancement Register Bit Functionality
Bit Function
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Reserved**
Reserved**
f
p
output
Power down
Counter load
MSEL output
f
c
output
Reserved**
Drives the M counter output onto the D
OUT
output.
Power down of all functions except programming interface.
Immediate and continuous load of counter programming.
Drives the internal dual modulus prescaler modulus select (MSEL) onto the D
OUT
output.
Drives the R counter output onto the D
OUT
output
Description
** Program to 0
PEREGRINE SEMICONDUCTOR CORP.
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Copyright
Peregrine Semiconductor Corp. 2003
Page 9 of 12
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