21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2308
3.3V Zero Delay Buffer
Select Input Decoding for PI6C2308 (-1, -1H, -2, -3, -4)
S2
0
0
1
1
S1
0
1
0
1
CLKA [1-4]
Hi- Z
Driven
Driven
Driven
CLKB [1-4]
Hi- Z
Hi- Z
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown
Y
N
Y
N
Select Input Decoding for PI6C2308-6
S2
0
0
1
1
S1
0
1
0
1
CLKA [1-4]
Hi- Z
Driven = Reference
Driven = PLL
Driven = PLL
CLKB [1-4]
Hi- Z
Driven = Reference/2
Driven = PLL
Driven = PLL/2
Output Source
PLL
Reference
PLL
PLL
PLL Shutdown
Y
Y
N
N
Available PI6C2308 Configurations
D e vice
PI6C2308- 1
PI6C2308- 1H
PI6C2308- 2
PI6C2308- 2
PI6C2308- 3
PI6C2308- 3
PI6C2308- 4
PI6C2308- 6
PI6C2308- 6
Fe e dback From
Bank A or Bank B
Bank A or Bank B
Bank A
Bank B
Bank A
Bank B
Bank A or Bank B
Bank A
Bank B
Bank A Fre que ncy
Reference
Reference
Reference
2X Reference
2X Reference
4X Reference
2X Reference
Reference
Reference or 2X Reference
Bank B Fre que ncy
Reference
Reference
Reference/2
Reference
Reference
2X Reference
2X Reference
Reference or Reference/2
Reference
2
PS8384D
06/26/01