PI6C2308-1HW 参数 Datasheet PDF下载

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PI6C2308

3.3V Zero Delay Buffer

Switching Characteristics

(5)

for Commercial Temperature Device

Parame te rs

t

1

t

2

N ame

O utput Frequency

Duty C ycle

(5)

= t

2

÷

t

1

(2308- 1H)

Duty C ycle = t

2

÷

t

1

(2308- 1, - 2, - 3, - 4, - 6)

Rise Time

(4)

@30pF

t

3

Rise Time

(4)

@15pF

Rise Time

(4)

@30pF (–1H)

Fall Time

(4)

@30pF

t

4

Fall Time

(4)

@15pF

Fall Time

(4)

@30pF (–1H)

O utput to O utput Skew

(4)

on same

bank (2308–1,–1H,–2,–3,–4,–6)

t

5

O utput Bank A to O utput Bank B

Skew

(4

) (2308–1,–1H,–4)

O utput Bank A to O utput Bank B

Skew

(4

) (2308–2,–3,–6)

t

6

(Phase

Error)

t

7

t

8

All outputs equally loaded, V

DD

/2

All outputs equally loaded, V

DD

/2

All outputs equally loaded, V

DD

/2

0

0

1

200

10 0

400

1. 0

ms

ps

Measured between 0.8V and 2.0V

Te s t Conditions

15pF to 30pF load

Measured at 1.4V, for high drive output

Measured at 1.4V, for normal drive output

M in.

10

45

40

50

50

Typ.

M ax. Units

134

55

60

2. 2

1. 5

1. 5

2. 2

1. 5

1. 2 5

200

200

400

± 200

600

V/ns

ps

ns

%

MHz

Input to O utput Delay, REF Rising Edge

Measured at V

DD

/2

to FBK Rising Edge

(4)

Device to Device Skew

(4)

O utput Slew

Rate

(4)

Measured at V

DD

/2 on the

FBK pins of devices

Measured between 0.8V and 2.0V on -

1H device using

Test C ircuit #2

Measured at 66.67 MHz,

loaded 30pF outputs

Measured at 133 MHz,

loaded 15pF outputs

Measured at 66.6 MHz,

loaded 30pF outputs

Stable power supply, valid clocks

presented on REF and FBK pins

t

J

C ycle- to- C ycle Jitter

(4)

(2308–1,–1H,–4)

C ycle- to- C ycle Jitter

(4)

(2308–2,–3,–6)

PLL Lock Time

(4)

t

J

t

LO CK

Notes:

1. Weak pull-down.

2. Weak pull-down on all outputs.

3. Weak pull-ups on these inputs.

4. REF and FBK inputs have a threshhold voltage of V

DD

/2.

5. For definition of t

1-8

, see Switching Waveforms on page 8.

5

PS8384D

06/26/01