REF - Input to CLKA/CLKB Delay (ps)
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PI6C2308
3.3V Zero Delay Buffer
Zero Delay and Skew Control
REF. Input to CLKA/CLKB Delay vs. Difference in Loading between FBK pin and CLKA/CLKB pins
800
600
400
200
0
-25
-200
-20
-15
-10
-5
0
5
10
15
20
25
-400
PI6C2308-1H
-600
-800
PI6C2308-1,2,3,4,6
-900
-1000
Output Load Difference: FBK Load - CLKA/CLKB Load (pF)
To close the feedback loop of the PI6C2308, the FBK pin can be
driven from any of the 8 available output pins. The output driving
the FBK pin will be driving a total load of 7pF plus any additional load
that it drives. The relative loading of this output (with respect to the
remaining outputs) can adjust the input-output delay. This is shown
in the graph above.
For applications requiring zero input-output delay, all outputs
including the one providing feedback should be equally loaded. If
input-output delay adjustments are required, use the above graph to
calculate loading differences between the feedback output and
remaining outputs.
Maximum Ratings
Supply Voltage to Ground Potential ...................0.5V to +7.0V
DC Input Voltage (Except REF) .................. 0.5V to V
DD
+0.5V
DC Input Voltage REF ................................................ 0.5 to 7V
Storage Temperature ........................................ 65ºC to +150ºC
Maximum Soldering Temperature (10 seconds) ................ 260ºC
Junction Temperature ....................................................... 150ºC
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .................................. >2000V
Operating Conditions
Parame te r
V
DD
T
A
C
L
C
IN
(Over operating range, T
A
= 0ºC to +70°C, V
CC
= 3.3V ±0.3V)
De s cription
Supply Voltage
Operating Temperature
(Ambient)
Load Capacitance
Input Capacitance
M in.
3.0
0
M ax.
3.6
70
30
7
Units
V
ºC
pF
3
PS8384D
06/26/01