PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
14.1.9
HEADER TYPE REGISTER – OFFSET 0Ch
Bit
23:16
Function
Header Type
Type
R/O
Description
Read as 01h to indicate that the register layout conforms to the
standard PCI-to-PCI bridge layout.
14.1.10
PRIMARY BUS NUMBER REGISTSER – OFFSET 18h
Bit
7:0
Function
Primary Bus
Number
Type
R/W
Description
Indicates the number of the PCI bus to which the primary interface
is connected. The value is set in software during configuration.
Reset to 0
14.1.11
SECONDARY BUS NUMBER REGISTER – OFFSET 18h
Bit
15:8
Function
Secondary Bus
Number
Type
R/W
Description
Indicates the number of the PCI bus to which the secondary
interface is connected. The value is set in software during
configuration.
Reset to 0
14.1.12
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h
Bit
23:16
Function
Subordinate Bus
Number
Type
R/W
Description
Indicates the number of the PCI bus with the highest number that is
subordinate to the bridge. The value is set in software during
configuration.
Reset to 0
14.1.13
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h
Bit
31:24
Function
Secondary
Latency Timer
Type
R/W
Description
Designated in units of PCI bus clocks. Latency timer checks for
master accesses on the secondary bus interfaces that remain
unclaimed by any target.
Reset to 0
14.1.14
I/O BASE REGISTER – OFFSET 1Ch
Bit
3:0
Function
32-bit Indicator
Type
R/O
Description
Read as 01h to indicate 32-bit I/O addressing
Page 81 of 111
APRIL 2006 – Revision 1.1
06-0057
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
