PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
14.1.24
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
Bit
31:0
Function
I/O Limit
Address, Upper
16-bits [31:16]
Type
R/W
Description
Defines the upper 16-bits of a 32-bit top address of an address range
for the bridge to determine when to forward I/O transactions from
one interface to the other.
Reset to 0
14.1.25
ECP POINTER REGISTER – OFFSET 34h
Bit
7:0
Function
Enhanced
Capabilities Port
Pointer
Type
R/O
Description
Enhanced capabilities port offset pointer. Read as DCh to indicate
that the first item resides at that configuration offset.
14.1.26
INTERRUPT LINE REGISTER – OFFSET 3Ch
Bit
7:0
Function
Interrupt Line
Type
R/W
Description
For POST to program to FFh, indicating that the PI7C8150A does not
implement an interrupt pin.
14.1.27
INTERRUPT PIN REGISTER – OFFSET 3Ch
Bit
15:8
Function
Interrupt Pin
Type
R/O
Description
Interrupt pin not supported on the PI7C8150A
14.1.28
BRIDGE CONTROL REGISTER – OFFSET 3Ch
Bit
16
Function
Parity Error
Response
Type
R/W
Description
Controls the bridge’s response to parity errors on the secondary
interface.
0: ignore address and data parity errors on the secondary interface
1: enable parity error reporting and detection on the secondary
interface
Reset to 0
Controls the forwarding of S_SERR_L to the primary interface.
0: disable the forwarding of S_SERR_L to primary interface
1: enable the forwarding of S_SERR_L to primary interface
Reset to 0
17
S_SERR_L
enable
R/W
Page 85 of 111
APRIL 2006 – Revision 1.1
06-0057
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
