PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
14.1.32
UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h
Bit
Function
Type
Description
0: Upstream memory is the entire range except the down stream
memory channel
1: Upstream memory is confined to upstream Memory Base and
Limit (See offset 50
th
and 54
th
for upstream memory range)
Reset to 0
Reserved. Returns 0 when read. Reset to 0
16
Upstream (S to
P) Memory Base
and Limit Enable
R/W
31:17
Reserved
R/O
14.1.33
SECONDARY BUS ARBITER PREEMPTION CONTROL
REGISTER – OFFSET 4Ch
Bit
Function
Type
Description
Controls the number of clock cycles after frame is asserted before
preemption is enabled.
1xxx: Preemption off
0000: Preemption enabled after 0 clock cycles
0001: Preemption enabled after 1 clock cycle
Secondary bus
arbiter
preemption
control
0010: Preemption enabled after 2 clock cycles
R/W
0011: Preemption enabled after 4 clock cycles
0100: Preemption enabled after 8 clock cycles
0101: Preemption enabled after 16 clock cycles
0110: Preemption enabled after 32 clock cycles
0111: Preemption enabled after 64 clock cycles
Reset to 0000
31:28
14.1.34
UPSTREAM (S TO P) MEMORY BASE REGISTER – OFFSET 50h
Bit
Function
Type
Description
0: 32 bit addressing
1: 64 bit addressing
Reset to 1
Controls upstream memory base address.
R/W
Reset to 00000000h
3:0
64 bit addressing
R/O
15:4
Upstream
Memory Base
Address
Page 89 of 111
APRIL 2006 – Revision 1.1
06-0057
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
