PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
14.1.35
UPSTREAM (S TO P) MEMORY LIMIT REGISTER – OFFSET 50h
Bit
Function
Type
Description
0: 32 bit addressing
1: 64 bit addressing
Reset to 1
Controls upstream memory limit address.
R/W
Reset to 000FFFFFh
19:16
64 bit addressing
R/O
31:20
Upstream
Memory Limit
Address
14.1.36
UPSTREAM (S TO P) MEMORY BASE UPPER 32-BITS REGISTER
– OFFSET 54h
Bit
31:0
Function
Upstream
Memory Base
Address
Type
R/W
Reset to 0
Description
Defines bits [63:32] of the upstream memory base
14.1.37
UPSTREAM (S TO P) MEMORY LIMIT UPPER 32-BITS
REGISTER – OFFSET 58h
Bit
31:0
Function
Upstream
Memory Limit
Address
Type
R/W
Reset to 0
Description
Defines bits [63:32] of the upstream memory limit
14.1.38
P_SERR_L EVENT DISABLE REGISTER – OFFSET 64h
Bit
0
Function
Reserved
Type
R/O
Description
Reserved. Returns 0 when read. Reset to 0
Controls PI7C8150A’s ability to assert P_SERR_L when it is unable
to transfer any read data from the target after 2
24
attempts.
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set.
1: P_SERR_L is not assert if this event occurs.
Reset to 0
Controls PI7C8150A’s ability to assert P_SERR_L when it is unable
to transfer delayed write data after 2
24
attempts.
Posted Write
Non-Delivery
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
1
Posted Write
Parity Error
R/W
2
R/W
Page 90 of 111
APRIL 2006 – Revision 1.1
06-0057
PERICOM [ PERICOM SEMICONDUCTOR CORPORATION ]
