PLL620-05/-06/-07/-08/-09
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)
Universal Low Phase Noise IC’s
FEATURES
•
•
100MHz to 200MHz Fundamental or 3
rd
Overtone Crystal.
Output range: 100 – 200MHz (no multiplication),
200 – 400MHz (2x multiplier), 400 – 700MHz (4x
multiplier), or 800MHz-1GHz(PLL620-09 only, 8x
multiplier).
CMOS (Standard drive PLL620-07 or Selectable
Drive PLL620-06), PECL (Enable low PLL620-08
or Enable high PLL620-05) or LVDS output
(PLL620-09).
Supports 3.3V-Power Supply.
Available in 16-Pin (TSSOP or 3x3mm QFN)
Note: PLL620-06 only available in 3x3mm.
Note: PLL620-07 only available in TSSOP.
PIN CONFIGURATION
(Top View)
VDD
XIN
XOUT
SEL3^
SEL2^
OE
GND
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL0^
SEL1^
GND
CLKC
VDD
CLKT
GND
GND
PLL 620-0x
•
•
•
DNC/
DRIVSEL*
SEL0^
10
DESCRIPTION
The PLL620-0x family of XO IC’s is specifically
designed to work with high frequency fundamental
and third overtone crystals. Their low jitter and low
phase noise performance make them well suited for
high frequency XO requirements. They achieve very
low current into the crystal resulting in better overall
stability.
XIN
XOUT
SEL2^
OE
13
14
15
16
12
11
SEL1^
9
VDD
8
7
6
5
GND
CLKC
VDD
CLKT
PLL620-0x
1
2
3
4
GND
GND
GND
BLOCK DIAGRAM
SEL
OE
PLL
(Phase
Locked
Loop)
^: Internal pull-up
*: PLL620-06 pin 12 is output drive select (DRIVSEL)
(0 for High Drive CMOS, 1 for Standard Drive CMOS)
The pin remains ‘Do Not Connect (DNC)’ for PLL620-05/07/08/09.
OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
Q
Q
X+
X-
Oscillator
Amplifier
PLL620-08
PLL620-05
PLL620-06
PLL620-07
PLL620-09
0
(Default)
1
0
1
(Default)
Output enabled
Tri-state
Tri-state
Output enabled
PLL by-pass
OE input: Logical states defined by PECL levels for PLL620-08
Logical states defined by CMOS levels for PLL620-05/-06/-
07/-09
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/01/05 Page 1
GND
PLL [ PHASELINK CORPORATION ]
