PLL620-05/-06/-07/-08/-09
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)
Universal Low Phase Noise IC’s
PIN DESCRIPTIONS
Name
VDD
XIN
XOUT
OE
GND
TSSOP*
Pin number
1, 12
2
3
6
7,8,9, 10, 14
3x3mm QFN*
Pin number
6,11
13
14
16
1,2,3,4,8
Type
P
I
I
I
P
+3.3V power supply.
Crystal input. See Crystal Specification on page 3.
Crystal output. See Crystal Specification on page 3.
Output enable.
Ground (except pin 12 on PLL620-06: DRIVSEL see below).
PLL620-06 only: Drive Select Input. This pin has an internal
pull-up that will default DRIVSEL to ‘1’ when not connect to
GND. CMOS output of PLL620-06 will be high drive CMOS
when DRIVSEL is set to ‘0’, and will be standard CMOS
otherwise. The pin remains ‘Do Not Connect (DNC)’ for
PLL620-05/07/08/09.
True output PECL (PLL620-08) or LVDS (PLL620-09)
(N/C for PLL620-07)
Complementary output PECL (PLL620-08) or LVDS (PLL620-
09)
(CMOS out for PLL620-07).
Multiplier selector pins. These pins have an internal pull-up
that will default SEL to ‘1’ when not connected to GND.
Description
DRIVSEL**
-
12
I
CLKT
CLKC
SEL0
SEL1
SEL2
SEL3
11
13
16
15
5
4
5
7
10
9
15
Not available
O
O
I
I
I
I
*
Note: PLL620-06 only available in 3x3mm QFN, PLL620-07 only available in TSSOP.
** Note: DRIVSEL on pin 12 on PLL620-06 only. The pin remains ‘Do Not Connect (DNC)’ for PLL620-05/07/08/09.
FREQUENCY SELECTION TABLE
SEL3
0
1
1
1
SEL2
0
0
1
1
SEL1
1
1
1
1
SEL0
1
1
0
1
Fin x 4
Fin x 2
No multiplication
Selected Multiplier
Fin x 8(PLL620-09 only)
Note:
SEL3 is not available (always “1”) in 3x3mm package
All pins have internal pull-ups (default value is 1). Connect to GND to set to 0.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/01/05 Page 2
PLL [ PHASELINK CORPORATION ]
