PLL620-05/-06/-07/-08/-09
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)
Universal Low Phase Noise IC’s
4. Jitter Specifications
PARAMETERS
Period jitter RMS
Period jitter peak-to-peak
Accumulated jitter RMS
Accumulated jitter peak-to-peak
Random Jitter
Integrated jitter RMS at 155MHz
Period jitter RMS
Period jitter peak-to-peak
Accumulated jitter RMS
Accumulated jitter peak-to-peak
Random Jitter
Integrated jitter RMS at 622MHz
CONDITIONS
At 155.52MHz, with capacitive decoupling
between VDD and GND. Over 10,000
cycles
At 155.52MHz, with capacitive decoupling
between VDD and GND. Over 1,000,000
cycles.
“RJ” measured on Wavecrest SIA 3000
Integrated 12 kHz to 20 MHz
At 622.08MHz, with capacitive decoupling
between VDD and GND. Over 10,000
cycles
At 622.08MHz, with capacitive decoupling
between VDD and GND. Over 1,000,000
cycles.
“RJ” measured on Wavecrest SIA 3000
Integrated 12 kHz to 20 MHz
MIN.
TYP.
2.5
18.5
2.5
24
2.5
0.3
11
45
11
24
3
1.6
MAX.
20
27
0.4
49
27
1.8
UNITS
ps
ps
ps
ps
ps
ps
ps
ps
5. Phase Noise Specifications
PARAMETERS
Phase Noise relative
to carrier
FREQUENCY
155.52MHz
622.08MHz
@10Hz
-75
-75
@100Hz
-95
-95
@1kHz
-125
-110
@10kHz
-140
-125
@100kHz
-145
-120
UNITS
dBc/Hz
6. CMOS Electrical Specifications
PARAMETERS
Output drive current
(High Drive)
Output drive current
(Standard Drive)
Output Clock Rise/Fall Time
(Standard Drive)
Output Clock Rise/Fall Time
(High Drive)
SYMBOL
I
OH
I
OL
I
OH
I
OL
CONDITIONS
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
0.3V ~ 3.0V with 15 pF load
0.3V ~ 3.0V with 15 pF load
MIN.
30
30
10
10
TYP.
MAX.
UNITS
mA
mA
mA
mA
2.4
1.2
ns
* Note: High Drive CMOS is available on PLL620-06 through DRIVSEL selector input on pin 12.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/01/05 Page 4
PLL [ PHASELINK CORPORATION ]
