(Preliminary)
1.8V-3.3V PicoTreo
TM
, 3-PLL, 200MHz, 5 Output Clock IC
PIN CONFIGURATION
XIN/FIN
CLK2/OEM^/PDB^
VDD
CLK0
1
PL613-05
SOP-8L
^ Denotes internal pull up
8
7
6
5
XOUT
VDD
CLK1
GND
GND
CLK4/CSEL^
CLK2/OEM^/PDB^
VDD
CLK3
1
2
3
4
5
PL613-05
10
9
8
7
6
XIN/FIN
XOUT
VDD
CLK1
CLK0
2
3
4
MSOP-10L
PACKAGE PIN ASSIGNMENT
Name
GND
CLK4/CSEL
CLK2/OEM/PDB
VDD
CLK3
CLK0
CLK1
XOUT
XIN/FIN
Package Pin #
MSOP-10L SOP-8L
1
2
3
4, 8
5
6
7
9
10
5
-
2
3, 7
-
4
6
8
1
Type
P
B*
B*
P
O
B*
O
O
I
GND connection
- Programmable Clock (CLK4) output or
- Configuration Switching input
- Programmable Clock (CLK2) output, or
- Output Enable Master (OEM) for all clock outputs, or
- Power Down mode (PDB) input
VDD connection
Programmable Clock (CLK3) output
Programmable Clock (CLK0) output
Programmable Clock (CLK1) output
Crystal output pin. Do Not Connect when using FIN
Crystal or Reference Clock input
Description
* Note:
All bidirectional buffers (I/Os) incorporate an internal 60KΩ
pull up resistor
except when PDB mode is used. In
configurations that use PDB, the PDB pin will have a 10MΩ pull up resistor.
KEY PROGRAMMING PARAMETERS
CLK[ 0:4 ]
Output Frequency
CLK[0]
F
VCO2
/ P
CLK[1,2]
F
VCOx
/ (P*(1,2,4,8)) or F
REF
/ (P*(1,2,4,8))
CLK[3]
F
VCO2
/ (P*(1,2,4,8)) or F
REF
/ (P*(1,2,4,8))
CLK[4]
F
VCO3
/ P or F
REF
/ P
Where F
VCO
= F
REF
* M / R
M = 11 bit
R = 8 bit
P = 5 bit (Odd/Even Divider)
Output Drive Strength
Each output has
three optional drive
strengths to choose
from. They are:
Low: 4mA
Std: 8mA (default)
High:16mA
Programmable Input/Output
Most pins are multi-function I/Os and can be
configured as:
OEM – (Master OE controlling all outputs)
CSEL – (Device Configuration Switching)
PDB – (Power Down)
CLK[0:4] – (Output)
HiZ or Active Low disabled state
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 7/2/07 Page 2
PLL [ PHASELINK CORPORATION ]
