(Preliminary)
1.8V-3.3V PicoTreo
TM
, 3-PLL, 200MHz, 5 Output Clock IC
On-The-Fly Configuration Switching (CSEL)
The PL613-05 can be programmed to allow switching
between 2 different configurations, allowing for
changes in the output frequency and other feature
changes. Many applications (i.e. video/audio) can use
the same design footprint, but allow for configuration
switching, adhering to various standards. CSEL is
used to make the switching selection. This pin
incorporates a 60kΩ
pull up resistor
for normal
operating condition. The logic for configuration
switching of the programmed parts is shown below:
CSEL
0
1
Programmed
Configuration
0
1(Default)
Note: Typical enable time is 100µs
.
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination
Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this
equals ringing!
- Long trace = Transmission Line. Without proper
termination this will cause reflections ( looks like
ringing ).
- Design long traces as “striplines” or “microstrips”
with defined impedance.
- Match trace at one side to avoid reflections
bouncing back and forth.
Decoupling and Power Supply
Considerations
- Place decoupling capacitors as close as possible to
the VDD pin(s) to limit noise from the power supply
- Multiple VDD pins should be decoupled separately
for best performance.
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency
dependant. Typical values to use are 0.1F for
designs using crystals < 50MHz and 0.01F for
designs using crystals > 50MHz.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 7/2/07 Page 4
PLL [ PHASELINK CORPORATION ]
