RELEASED
Data Sheet
PMC-2000164
ISSUE 3
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
ENHANCED TT1™ SWITCH FABRIC
4.4.2
Crossbar Register Descriptions
Read and Clear means that reading the register causes it to be cleared (reset to zero).
All bits labeled as Reserved should be set to 0.
4.4.2.1
Symbol:
Status
XSTS
Address Offset: 00000h
Default Value: 40000000h
Access:
Read Only
The top 8 bits are device_id [3:0] and revision [3:0]. OOB interrupt bits are [1:0] (high, low), all other bits
are reserved.
Bits
31:28
27:24
23:2
1
0
Device Revision Number.
Reserved.
High Priority Interrupt.
1 = There is an outstanding high priority interrupt. One of the bits in
the General Interrupt Register is set, and is enabled via its corresponding high priority mask.
Low Priority Interrupt.
1 = There is an outstanding low priority interrupt. One of the bits in the
General Interrupt Register is set, and is enabled via its corresponding low priority mask.
Description
Device ID Number.
Identifies the specific device.
4.4.2.2
Symbol:
Control/Reset
XMODERS
Address Offset: 00004h
Default Value: 00000004h
Access:
Read/Write
This register configures the number of ports supported by this Crossbar. It also resets the entire device,
equivalent to a hardware reset.
Bits
31-3
Reserved.
Description
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
229
PMC [ PMC-SIERRA, INC ]
