ZM7300G Series Digital Power Manager
Data Sheet
8.4
I
2
C Interface
Conditions/Description
Input low voltage
Input high voltage
Input hysteresis
Output low voltage, I
SINK
=3mA
Rise time for SDA and SCL
Output fall time from ViHmin to ViLmax
Input current each I/O pin, 0.1V
DD
<V
i
<0.9V
DD
Capacitance for each I/O pin
SCL clock frequency
External pull-up resistor
Hold time (repeated) START condition
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
Data setup time
Setup time for STOP condition
Bus free time between a STOP and START condition
2
Parameter
ViL
ViH
Vhys
VoL
t
r
t
of
Ii
Ci
f
SCL
R
PU
t
HDSTA
t
LOW
t
HIGH
t
SUSTA
t
HDDAT
t
SUDAT
t
SUSTD
t
SUF
R
PU
t
HDSTA
t
LOW
t
HIGH
t
SUSTA
t
HDDAT
t
SUDAT
t
SUSTD
t
SUF
Min
-0.5
0.7·VDD
0.05·VDD
0
1
20+0.1C
b
20+0.1C
b1
-10
0
1
4.0
4.7
4.0
4.7
0
250
4.0
4.7
1
0.6
1.3
0.6
0.6
0
100
0.6
1.3
Nom
Max
0.3·VDD
VDD+0.5
0.4
300
250
10
10
400
1000/C
b1
Units
V
V
V
V
ns
ns
μA
pF
kHz
kΩ
μs
μs
μs
μs
μs
ns
μs
μs
kΩ
μs
μs
μs
μs
μs
ns
μs
μs
Standard-Mode I
2
C (f
SCL
≤
100kHz)
3.45
Fast-Mode
I C
(100kHz < f
SCL
≤
400kHz)
External pull-up resistor
Hold time (repeated) START condition
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
Data setup time
Setup time for STOP condition
Bus free time between a STOP and START condition
300/C
b1
0.9
______________________________________
1
C
b
– bus capacitance in pF, typically from 10pF to 400pF
t
o
f
t
HIG
H
t
LO
W
t
r
t
LO
SCL
t
SUST
A
W
t
HDST
A
t
HDDA
t
SUDA
T
T
t
SUST
O
SDA
t
BU
F
Figure 2. I C Timing Parameters
2
ZD-00896 Rev. 5.1, 13-Jul-10
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