ZM7300G Series Digital Power Manager
Data Sheet
The DPM can also trigger an optional crowbar circuit and provide undervoltage and overvoltage
protections of the intermediate bus voltage. In addition, the DPM can be controlled by a host system via
the interrupt inputs, RES_N and the ACFAIL_N inputs.
10
Description
The ZM7300 series DPMs perform translation between the I
2
C interface connected to a host system or
the Graphical User Interface and the SD communication bus connected to Z-series POL converters. In
addition, DPMs carry out programming, monitoring, data storage, POL group management, hot-swap
control, protection, and control and monitoring of auxiliary devices.
The DPMs can be controlled via the GUI or directly via the I
2
C bus by using specific commands
described in the “DPM Programming Manual”.
DPM Memory
The DPM memory consists of RAM and non-volatile memory (Flash). The RAM is used for
programming perations and manipulation of the various blocks of configuration, setup, status, and
monitoring registers. The non-volatile memory is used to store programming and configuration data.
The DPM memory includes DPM registers, POL setup registers, monitoring data, and user memory as
shown in Figure 4. Setup registers for the DPM and the POL converters are protected by CRCs that are
checked during programming of POL converters and at the power-up of the DPM.
10.1
The LCK_N pin and the write protection register WP limit the write access to the memory blocks in the
DPM and POL converters. The WP register content is defaulted to write protect upon powering up the
DPM.
Figure 4. DPM Memory and Write Protection
ZD-00896 Rev. 5.1, 13-Jul-10
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