ZM7300G Series Digital Power Manager
Data Sheet
10.1.1 Write Protection
There are hardware-based and software-based memory write protections. The hardware protection
takes precedence over the software protection.
10.1.1.1
Hardware Protection
The LCK_N pin enables the hardware memory write protection. If the pin is pulled low, the hardware
lock is active and the memory blocks are then read-only. I
2
C write commands to the DPM return an
error code (0x00). The write commands to the POL converters bypassing the DPM are also disabled. If
the pin is left floating, the hardware lock is disabled and the software write protection is active.
10.1.1.2
Software Protection
The software write protection allows users to protect the various memory blocks from being overwritten
through the I
2
C bus. At the power-up the WP register is defaulted to write protect.
The software write protection can be disabled by checking appropriate boxes in the Write Protections
window shown in Figure 5 or via the I
2
C bus by writing directly into the register. The write protections
are automatically restored when the DPM’s input power is recycled.
Figure 5. GUI Write Protections Window
10.1.2 DPM Registers
The DPM setup registers occupy 70 bytes and contain all necessary information to set up the DPM
functionality, define POL converters and Auxiliary Devices, group membership and behavior, margining,
interrupt configurations, etc.
The DPM registers are listed in
Table 1
. The table relates to the DPM model number ZM7332 capable
of supporting up to 32 POL converters. For other DPM models some of the registers and/or bits in the
registers are not activated depending on the number of supported POLs/Groups/Interrupts/Parallel
Buses for the specific DPM. Writing into an unsupported register or bit will have no effect, reading from
an unsupported register or bit will return an error code (0x00).
ZD-00896 Rev. 5.1, 13-Jul-10
www.power-one.com
Page 9 of 33
POWER-ONE [ POWER-ONE ]
