October 2006
rev 2.2
Select Input Decoding for ASM5P2309A
S2
0
0
1
1
Notes:
ASM5P2305A
ASM5P2309A
S1
0
1
0
1
Clock A1 - A4
Three-state
Driven
Driven
Driven
Clock B1 - B4
Three-state
Three-state
Driven
Driven
CLKOUT
1
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL
Shut-Down
N
N
Y
N
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and the
output.
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the CLKOUT pin is
the internal feedback to the PLL, its relative loading can
adjust the input-output delay.
For applications requiring zero input-output delay, all
outputs, including CLKOUT, must be equally loaded. Even
if CLKOUT is not used, it must have a capacitive load equal
to that on other outputs, for obtaining zero-input-output
delay.
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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