November 2006
rev 1.5
ASM5P2308A
Pin Configuration
REF 1
CLKA1 2
CLKA2 3
V
DD
4
ASM5P2308A
GND 5
CLKB1 6
CLKB2 7
S2
8
16 FBK
15 CLKA4
14 CLKA3
13 V
DD
12 GND
11 CLKB4
10 CLKB3
9
S1
Pin Description for ASM5P2308A
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
REF
3
4
4
Description
Input reference frequency, 5V tolerant input
Buffered clock output, bank A
Buffered clock output, bank A
3.3V supply
Ground
Buffered clock output, bank B
Buffered clock output, bank B
Select input, bit 2
Select input, bit 1
CLKA1
CLKA2
V
DD
GND
CLKB1
4
CLKB2
4
S2
S1
5
5
4
4
CLKB3
CLKB4
GND
V
DD
Buffered clock output, bank B
Buffered clock output, bank B
Ground
3.3V supply
Buffered clock output, bank A
Buffered clock output, bank A
PLL feedback input
CLKA3
4
CLKA4
FBK
4
Notes:
3. Weak pull-down.
4. Weak pull-down on all outputs.
5. Weak pull-up on these inputs.
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
