September 2006
rev 0.3
Pin Diagram
PCS2P3805A
V
CCA
OA
1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
V
CCB
OB
1
OB
2
OB
3
GND
B
OB
4
OB
5
MON
OE
B
IN
B
OA
2
OA
3
GND
A
OA
4
OA
5
GND
Q
OE
A
IN
A
PCS2P3805A
16
15
14
13
12
11
Pin Description
Pin #
9,12
10,11
2,3,4,6,7
19,18,17,15,14
1
20
5
16
8
13
Pin Names
OE
A
, OE
B
¯¯ ¯¯
IN
A
, IN
B
OA
1
-OA
5
OB
1
-OB
5
V
CCA
V
CCB
GND
A
GND
B
GND
Q
MON
Description
3-State Output Enable Inputs (Active LOW)
Clock Inputs
Clock Outputs
Clock Outputs
Power supply for Bank A
Power supply for Bank B
Ground for Bank A
Ground for Bank B
Ground
Monitor Output
3.3V CMOS Buffer Clock Driver
Notice: The information in this document is subject to change without notice.
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