September 2006
rev 0.4
AC Electrical Specifications
(VDD = 2.5V ± 5%, T
A
= -40°C to +85°C)
1
Parameter
f
VCO
PCS5I9774
Description
VCO Frequency
Condition
÷8 Feedback
÷12 Feedback
÷16 Feedback
Min
200
25
16.6
12.5
8.3
6.3
4.2
0
25
Typ
Max
400
50
33.3
25
16.6
12.5
8.3
200
75
1.0
Unit
MHz
f
in
Input Frequency
÷24 Feedback
÷32 Feedback
÷48 Feedback
Bypass mode
(PLL_EN = 0)
MHz
f
refDC
t
r
, t
f
Input Duty Cycle
TCLK Input Rise/FallTime
0.7V to 1.7V
÷4 Output
÷8 Output
%
nS
50
25
16.6
12.5
8.3
45
100
50
33.3
25
16.6
55
0.75
100
150
150
pS
200
10
10
0.5 -1.0
nS
nS
MHz
100
250
100
125
1
pS
pS
pS
mS
%
nS
pS
pS
MHz
f
MAX
Maximum Output Frequency
÷12 Output
÷16 Output
÷24 Output
DC
t
r
, t
f
t(φ)
t
sk(O)
t
sk(B)
t
PLZ, HZ
t
PZL, ZH
BW
t
JIT(CC)
t
JIT(PER)
t
JIT(φ)
t
LOCK
Output Duty Cycle
Output Rise/Fall times
Propagation Delay
(static phase offset)
Output-to-Output Skew
Bank-to-Bank Skew
Output Disable Time
Output Enable Time
PLL Closed Loop Bandwidth
(–3 dB)
Cycle-to-Cycle Jitter
Period Jitter
I/O Phase Jitter
Maximum PLL Lock Time
Same frequency
Multiple frequencies
0.7V to 1.8V
TCLK to FB_IN, does
not include jitter
Skew within Bank
Banks at same
frequency
Banks at different
frequency
0.1
-100
Note: 1. AC characteristics apply for parallel output termination of 50Ω to V
TT
. Outputs are at same supply voltage unless otherwise stated. Parameters are
guaranteed by characterization and are not 100% tested.
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
7 of 12
PULSECORE [ PulseCore Semiconductor ]
