September 2006
rev 0.4
AC Electrical Specifications
(VDD = 3.3V ± 5%, T
A
= -40°C to +85°C)
1
Parameter
f
VCO
f
in
PCS5I9774
Description
VCO Frequency
Input Frequency
Condition
÷8 Feedback
÷12 Feedback
÷16 Feedback
÷24 Feedback
÷32 Feedback
÷48 Feedback
Bypass mode
(PLL_EN = 0)
Min
200
25
16.6
12.5
8.3
6.25
4.2
0
25
Typ
Max
500
62.5
41.6
31.25
20.8
15.625
10.4
200
75
1.0
125
62.5
41.6
31.25
20.8
55
1.0
100
150
150
225
250
10
10
Unit
MHz
MHz
f
refDC
t
r
, t
f
f
MAX
Input Duty Cycle
TCLK Input Rise/FallTime
Maximum Output Frequency
0.8V to 2.0V
÷4 Output
÷8 Output
÷12 Output
÷16 Output
÷24 Output
%
nS
50
25
16.6
12.5
8.3
45
0.1
-100
MHz
DC
tr, tf
t
(φ)
t
sk(O)
t
sk(B)
Output Duty Cycle
Output Rise/Fall times
Propagation Delay
(static phase offset)
Output-to-Output Skew
Bank-to-Bank Skew
0.8V to 2.4V
TCLK to FB_IN, same
VDD, does not include jitter
Skew within Bank
Banks at same voltage,
same frequency
Banks at same voltage,
different frequency
Banks at different voltage
%
nS
pS
pS
pS
t
PLZ, HZ
t
PZL, ZH
BW
t
JIT(CC)
Output Disable Time
Output Enable Time
PLL Closed Loop Bandwidth
(–3dB)
Cycle-to-Cycle Jitter
0.5 - 1.0
Same frequency
Multiple frequencies
nS
nS
MHz
150
300
100
150
1
pS
pS
pS
mS
t
JIT(PER)
t
JIT(φ)
t
LOCK
Period Jitter
I/O Phase Jitter
Maximum PLL Lock Time
I/O at same VDD
Note: 1. AC characteristics apply for parallel output termination of 50Ω to V
TT
. Outputs are at same supply voltage unless otherwise stated. Parameters are
guaranteed by characterization and are not 100% tested.
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
8 of 12
PULSECORE [ PulseCore Semiconductor ]
