P4C1024
AC CHARACTERISTICS—WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Parameter
-15
-20
-25
-35
-45
-55
-70
-85
-100
-120
Unit
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
20
15
15
0
15
0
8
0
8
3
3
10
3
25
18
20
0
18
0
10
0
11
3
35
22
25
0
22
0
15
0
15
3
45
30
35
0
25
0
20
0
18
3
55
35
45
0
30
0
25
0
20
3
70
45
60
0
40
0
30
0
25
3
85
50
70
0
45
0
35
0
30
3
100
60
85
0
55
0
45
0
40
3
120
75
100
0
70
0
60
0
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time 15
Chip Enable
Time to End of
Write
Address Valid to
End of Write
Address Set-up
Time
Write Pulse
Width
Address Hold
Time
Data Valid to
End of Write
Date Hold Time
Write Enable to
Output in High Z
Output Active
from End of
Write
12
12
0
12
0
7
0
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)
(11)
WE
Notes:
11.
CE
1
and
WE
must be LOW, and CE
2
HIGH for WRITE cycle.
12.
OE
is LOW for this WRITE cycle to show t
WZ
and t
OW
.
13. If
CE
1
goes HIGH, or CE
2
goes LOW, simultaneously with
WE
HIGH,
the output remains in a high impedance state.
14. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM124
REV A
Page 6 of 14
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
