P4C148/P4C149
AC CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym
t
RC
t
AA
t
AC
t
AC
t
OH
t
LZ
t
HZ
t
RCS
t
RCH
t
PU
t
PD
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time (P4C148)
Chip Enable Access Time (P4C149)
Output Hold from Address Change
Chip Enable to Output in Low Z (P4C149)
Chip Disable to Output in High Z (P4C149)
Read Command Setup Time
Read Command Hold Time
Chip Enable to Power Up Time (P4C148)
Chip Disable to Power Down Time (P4C148)
0
0
0
10
3
2
4
0
0
0
12
-10
-12
-15
-20
-25
-35
-45
-55
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
10
12
15
20
25
35
45
55
10
10
8
3
2
5
0
0
0
15
12
12
10
3
2
6
0
0
0
20
15
15
12
3
2
8
0
0
0
25
20
20
14
3
2
10
0
0
0
35
25
25
15
3
2
14
0
0
0
45
35
35
20
3
2
18
0
0
0
55
45
45
20
3
2
20
55
55
25
TIMING WAVEFORM OF READ CYCLE
TIMING WAVEFORM OF READ CYCLE NO. 2
(6)
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to MAXIMUM rating condi-
tions for extended periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet
per minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5.
CE
is LOW and
WE
is HIGH for READ cycle.
6.
WE
is HIGH, and address must be valid prior to or coincident with
CE
transition LOW.
7. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is
sampled and not 100% tested.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM104
REV B
Page 3 of 10
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
