P4C422
FUNCTIONAL DESCRIPTION
An active LOW write enable (WE) controls the writing/
reading operation of the memory. When the chip select
one (CS
1
) and the write enable (WE) are LOW and the chip
select two (CS
2
) is HIGH, the information on data inputs
(D
0
through D
3
) is written into the addressed memory word
and preconditions the output circuitry so that true data is
present at the outputs when the write cycle is complete.
This preconditioning operation insures minimum write
recovery times by eliminating the “write recovery glitch.”
Reading is performed with chip selct one (CS
1
) LOW, chip
select two (CS
2
) HIGH, write enable (WE) HIGH and
output enable (OE) LOW. The information stored in the
addressed word is read out on the noninverting outputs
(O
0
through O
3
). The outputs of the memory go to an
inactive high impedance state whenever chip select one
(CS
1
) is HIGH, or during the write operation when write
enable (WE) is LOW.
TRUTH TABLE
Mode
Standby
Standby
D
OUT
Disabled
Read
Write
CS
2
L
X
H
H
H
CS
1
X
H
L
L
L
WE
X
X
X
H
L
OE
X
X
H
L
X
Output
High Z
High Z
High Z
D
OUT
High Z
Notes:
H
L
X
HIGH Z
= HIGH
= Low
= Don't Care
= Implies outputs are disabled or off. This condition
is defined as high impedance state for the
P4C422.
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10% except as noted, All Temperature Ranges)
(2)
Sym.
t
RC
t
ACS
t
ZRCS
t
AOS
t
ZROS
t
AA
Parameter
Read Cycle Time
(5)
Chip Select Time
(5)
Chip Select to High-Z
(6)
Output Enable Time
Output Enable to High-Z
(6)
Address Access Time
(5)
-10*
12
7.5
8
7.5
8
10
-12
-15
15
8
8
12
8
12
15
-20
20
12
15
12
15
20
-25
-35
35
Min Max Min Max Min Max Min Max Min Max Min Max
12
25
15
20
15
20
25
25
30
25
30
35
Unit
ns
ns
ns
ns
ns
ns
10
8
10
12
*V
CC
= 5V ± 5%
TIMING WAVEFORM OF READ CYCLE
Document #
SRAM101
REV. A
Page 3 of 10
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
