Internet Data Sheet
HYB18TC256[80/16]0BF
256-Mbit Double-Data-Rate-Two SDRAM
Chip Configuration for
×8
components, PG-TFBGA-60 (top view)
FIGURE 1
Notes
1.
2.
3.
4.
RDQS / RDQS are enabled by EMRS(1) command.
If RDQS / RDQS is enabled, the DM function is disabled
When enabled, RDQS & RDQS are used as strobe signals during reads.
V
DDL
and
V
SSDL
are power and ground for the DLL.
V
DDL
is connected to
V
DD
on the device.
V
DD
,
V
DDQ
,
V
SSDL
,
V
SS
, and
V
SSQ
are isolated on the device.
5. Ball position L8 is A13 for 512-Mbit and is Not Connected on 256-Mbit.
Rev. 1.3, 2007-05
07182006-DD60-22E6
9