Internet Data Sheet
HYB18TC256[80/16]0BF
256-Mbit Double-Data-Rate-Two SDRAM
2
2.1
Configuration
Chip Configuration for PG-TFBGA-60
This chapter contains the chip configuration, addressing.
The chip configuration of a DDR2 SDRAM is listed by function in
The abbreviations used in the Ball# columns are
explained in
and
respectively. The ball numbering for the FBGA package is depicted in figures.
TABLE 6
Chip Configuration of DDR2 SDRAM
Ball#
Name
Ball
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Address Signal 12:0, Address Signal 10/Autoprecharge
Chip Select
Bank Address Bus 1:0
Clock Enable
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Function
Clock Signals
×8
organization
E8
F8
F2
F7
G7
F3
G8
G2
G3
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
CK
CK
CKE
RAS
CAS
WE
CS
BA0
BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
Clock Signal CK, CK
Control Signals
×8
organizations
Address Signals
×8
organizations
Rev. 1.3, 2007-05
07182006-DD60-22E6
6
QIMONDA [ QIMONDA AG ]
