Internet Data Sheet
HYB25DC512[800/160]C[E/F]
512-Mbit Double-Data-Rate SDRAM
1
Overview
This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main
characteristics.
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
Burst Lengths: 2, 4, or 8
CAS Latency: 2, 2.5, 3
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
RAS-lockout supported
t
RAP
=
t
RCD
7.8
µs
Maximum Average Periodic Refresh Interval
2.5 V (SSTL_2 compatible) I/O
V
DDQ
= 2.5 V
±
0.2 V
V
DD
= 2.5 V
±
0.2 V
PG-TFBGA-60 and PG-TSOPII-66 packages
RoHS Compliant Products
• Double data rate architecture: two data transfers per clock
cycle
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is center-
aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
TABLE 1
Performance
Part Number Speed Code
Speed Grade
Max. Clock Frequency
Component
@CL3
@CL2.5
@CL2
–5
DDR400B
–6
DDR333
166
166
133
Unit
—
MHz
MHz
MHz
f
CK3
f
CK2.5
f
CK2
200
166
133
Rev. 1.3, 2006-12
03292006-W2FE-ELDX
3
QIMONDA [ QIMONDA AG ]
