Internet Data Sheet
HYB25DC512[800/160]C[E/F]
512-Mbit Double-Data-Rate SDRAM
2
Chip Configuration
The pin configuration of a DDR SDRAM is listed by function in
The abbreviations used in the Pin#/Buffer# column are
explained in
and
respectively. The pin numbering for FBGA is depicted in
and that of the TSOP
package in
TABLE 3
Ball Configuration of DDR SDRAM
Ball#/Pin#
Clock Signals
G2, 45
G3, 46
H3, 44
Control Signals
H7, 23
G8, 22
G7, 21
H8, 24
J8, 26
J7, 27
K7, 29
L8, 30
L7, 31
M8, 32
M2, 35
L3, 36
L2, 37
K3, 38
K2, 39
J3, 40
K8, 28
J2, 41
H2, 42
RAS
CAS
WE
CS
BA0
BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
NC
F9, 17
A13
NC
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
NC
I
NC
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
SSTL
—
Address Signal 12
Note: Module based on 256 Mbit or larger dies
Note: Module based on 128 Mbit or smaller dies
Address Signal 13
Note: 1 Gbit based module
Note: Module based on 512 Mbit or smaller dies
Address Bus 11:0
Row Address Strobe
Column Address Strobe
Write Enable
Chip Select
Bank Address Bus 2:0
CK1
CK1
CKE
I
I
I
SSTL
SSTL
SSTL
Clock Signal
Complementary Clock Signal
Clock Enable
Name
Pin
Type
Buffer
Type
Function
Address Signals
Rev. 1.3, 2006-12
03292006-W2FE-ELDX
5
QIMONDA [ QIMONDA AG ]
