Internet Data Sheet
HYS[64/72]T[16/32/64]0xxHU–[2.5/../5]–A
Unbuffered DDR2 SDRAM Modules
2
Pin Configuration
The pin configuration of the Unbuffered DDR2 SDRAM DIMM is listed by function in
(240 pins). The abbreviations used
in columns Pin and Buffer Type are explained in
and
respectively. The pin numbering is depicted in
for non-ECC modules (×64) and
for ECC modules
(×72).
TABLE 5
Pin Configuration of UDIMM
Ball No.
Clock Signals
185
137
220
186
138
221
52
171
CK0
CK1
CK2
CK0
CK1
CK2
CKE0
CKE1
NC
Control Signals
193
76
S0#
S1#
NC
192
74
73
Address Signals
71
190
54
BA0
BA1
BA2
NC
I
I
I
NC
SSTL
SSTL
SSTL
—
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
Not Connected
Less than 1Gb DDR2 SDRAMS
Bank Address Bus 1:0
RAS
CAS
WE
I
I
NC
I
I
I
SSTL
SSTL
—
SSTL
SSTL
SSTL
Chip Select Rank 1:0
Note: 2 Ranks module
Not Connected
Note: 1 Rank module
Row Address Strobe
Column Address Strobe
Write Enable
I
I
I
I
I
I
I
I
NC
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
Clock Enable Rank 1:0
Note: 2 Ranks module
Not Connected
Note: 1 Rank module
Clock Signals 2:0, Complement Clock Signals 2:0
Name
Pin
Type
Buffer
Type
Function
Rev. 1.41, 2006-11
03062006-0GN5-WTPW
6
QIMONDA [ QIMONDA AG ]
