Internet Data Sheet
HYS[64/72]T256xxxHU–[3/…/5]–A
Unbuffered DDR2 SDRAM Modules
3.3.2
AC Timing Parameters
List of AC timing parameter tables.
•
•
•
TABLE 17
Timing Parameter by Speed Grade - DDR2–667
Parameter
Symbol
DDR2–667
Min.
Max.
+450
+400
0.52
0.52
8000
––
––
—
—
ps
ps
9)
10)11)
Unit
Note
1)2)3)4)5)6)7)
8)
t
AC
DQS output access time from CK / CK
t
DQSCK
Average clock high pulse width
t
CH.AVG
Average clock low pulse width
t
CL.AVG
Average clock period
t
CK.AVG
DQ and DM input setup time
t
DS.BASE
DQ and DM input hold time
t
DH.BASE
Control & address input pulse width for each input
t
IPW
DQ and DM input pulse width for each input
t
DIPW
Data-out high-impedance time from CK / CK
t
HZ
DQS/DQS low-impedance time from CK / CK
t
LZ.DQS
DQ low impedance time from CK/CK
t
LZ.DQ
DQS-DQ skew for DQS & associated DQ signals
t
DQSQ
CK half pulse width
t
HP
DQ output access time from CK / CK
DQ hold skew factor
DQ/DQS output hold time from DQS
Write command to DQS associated clock edges
–450
–400
0.48
0.48
3000
100
175
0.6
0.35
—
t
CK.AVG
t
CK.AVG
ps
ps
ps
12)13)14)
t
CK.AVG
t
CK.AVG
ps
ps
ps
ps
ps
ps
ps
nCK
17)
18)
t
AC.MIN
2 x
t
AC.MIN
—
Min(
t
CH.ABS
,
t
CL.ABS
)
—
t
AC.MAX
t
AC.MAX
t
AC.MAX
240
__
340
—
+ 0.25
—
—
—
—
0.6
—
—
—
1.1
0.6
70000
t
QHS
t
QH
WL
19)
20)
t
HP
–
t
QHS
RL–1
– 0.25
0.35
0.35
0.2
0.2
0.4
0.35
200
275
0.9
0.4
45
DQS latching rising transition to associated clock
t
DQSS
edges
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Write postamble
Write preamble
Address and control input setup time
Address and control input hold time
Read preamble
Read postamble
Active to precharge command
t
CK.AVG
t
CK.AVG
t
CK.AVG
t
CK.AVG
t
CK.AVG
t
CK.AVG
t
CK.AVG
ps
ps
21)
t
DQSH
t
DQSL
t
DSS
t
DSH
t
WPST
t
WPRE
t
LS.BASE
t
LH.BASE
t
RPRE
t
RPST
t
RAS
22)23)
25)26)
28)
t
CK.AVG
t
CK.AVG
ns
Rev. 1.32, 2006-09
03062006-5RK8-1X8J
21
QIMONDA [ QIMONDA AG ]
