Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
TABLE 14
Speed Grade Definition Speed Bins for DDR2–533C
Speed Grade
QAG Sort Name
CAS-RCD-RP latencies
Parameter
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Symbol
DDR2–533C
–3.7
4–4–4
Min.
5
3.75
3.75
45
60
15
15
Max.
8
8
8
70000
—
—
—
Unit
Note
t
CK
—
ns
ns
ns
ns
ns
ns
ns
1)2)3)4)
t
CK
t
CK
t
CK
t
RAS
t
RC
t
RCD
t
RP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is recognized as low.
4) The output timing reference voltage level is
V
TT
.
5)
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
t
REFI
.
Rev. 1.0, 2006-11
11172006-DXYK-2PPW
16
QIMONDA [ QIMONDA AG ]
