Internet Data Sheet
HYS72T[64/128]3x0HP–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Pin No.
161
162
167
168
Data Strobe Bus
7
6
16
15
28
27
37
36
84
83
93
92
105
104
114
113
46
45
125
126
134
135
146
147
155
156
202
203
211
212
223
224
232
Name
CB4
CB5
CB6
CB7
DQS0
DQS0
DQS1
DQS1
DQS2
DQS2
DQS3
DQS3
DQS4
DQS4
DQS5
DQS5
DQS6
DQS6
DQS7
DQS7
DQS8
DQS8
DQS9
DQS9
DQS10
DQS10
DQS11
DQS11
DQS12
DQS12
DQS13
DQS13
DQS14
DQS14
DQS15
DQS15
DQS16
Pin
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Function
Check Bits 7:0
Check Bit Input / Output pins
Note: NC on Non-ECC module
Data Strobes 17:0
The data strobes, associated with one data byte, sourced with data
transfers. In Write mode, the data strobe is sourced by the controller
and is centered in the data window. In Read mode the data strobe is
sourced by the DDR2 SDRAM and is sent at the leading edge of the
data window. DQS signals are complements, and timing is relative to
the crosspoint of respective DQS and DQS. If the module is to be
operated in single ended strobe mode, all DQS signals must be tied on
the system board to
V
SS
through a 20
Ω
to 10 kΩ resistor and DDR2
SDRAM mode registers programmed appropriately.
Note: See block diagram for corresponding DQ signals
Rev. 1.22, 2007-06
07042006-834B-Z31V
10
QIMONDA [ QIMONDA AG ]
