Internet Data Sheet
HYS72T[64/128]3x0HP–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
2
2.1
Pin Configuration and Block Diagrams
Pin Configuration
and
respectively. The pin numbering is depicted in
This chapter contains the pin configuration and block diagrams.
The pin configuration of the Registered DDR2 SDRAM DIMM
is listed by function in
(240 pins). The abbreviations
used in columns Pin and Buffer Type are explained in
TABLE 5
Pin Configuration of RDIMM
Pin No.
Clock Signals
185
186
CK0
CK0
I
I
SSTL
SSTL
Clock Signal CK0, Complementary Clock Signal CK0
The system clock inputs. All address and command lines are sampled
on the cross point of the rising edge of CK and the falling edge of CK.
A Delay Locked Loop (DLL) circuit is driven from the clock inputs and
output timing for read operations is synchronized to the input clock.
Clock Enables 1:0
Activates the DDR2 SDRAM CK signal when HIGH and deactivates
the CK signal when LOW. By deactivating the clocks, CKE0 initiates
the Power Down Mode or the Self Refresh Mode.
Note: 2-Ranks module
Not Connected
Note: 1-Rank module
Chip Select
Enables the associated DDR2 SDRAM command decoder when LOW
and disables the command decoder when HIGH. When the command
decoder is disabled, new commands are ignored but previous
operations continue.
Rank 0 is selected by S0
Rank 1 is selected by S1
The input signals also disable all outputs (except CKE and ODT) of the
register(s) on the DIMM when both inputs are high. When S is HIGH,
all register outputs (except CK, ODT and Chip select) remain in the
previous state.
Note: 2-Ranks module
Not Connected
Note: 1-Rank module
Name
Pin
Type
Buffer
Type
Function
52
171
CKE0
CKE1
I
I
SSTL
SSTL
NC
Control Signals
193
76
S0
S1
NC
—
I
I
SSTL
SSTL
NC
NC
—
Rev. 1.22, 2007-06
07042006-834B-Z31V
6
QIMONDA [ QIMONDA AG ]
