Internet Data Sheet
HYS72T[64/128]3x0HP–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Pin No.
220
Name
S2
NC
Pin
Type
I
NC
I
NC
I
I
I
I
Buffer
Type
SSTL
Function
Rank 2 is selected by S2
—
SSTL
Rank 3 is selected by S3
NC
192
74
73
18
RAS
CAS
WE
RESET
—
SSTL
SSTL
SSTL
CMOS
Not Connected
Note: 1-Rank, 2-Ranks module
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
When sampled at the cross point of the rising edge of CK, and falling
edge of CK, RAS, CAS and WE define the operation to be executed by
the SDRAM.
Register Reset
The RESET pin is connected to the RST pin on the register and to the
OE pin on the PLL. When LOW, all register outputs will be driven LOW
and the PLL clocks to the DRAMs and the register(s) will be set to low-
level. The PLL will remain synchronized with the input clock.
Bank Address Bus 1:0
Selects internal SDRAM memory bank
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
Not Connected
Less than 1Gb DDR2 SDRAMS
Address Bus 12:0, Address Signal 10/AutoPrecharge
During a Bank Activate command cycle, defines the row address when
sampled at the crosspoint of the rising edge of CK and falling edge of
CK. During a Read or Write command cycle, defines the column
address when sampled at the cross point of the rising edge of CK and
falling edge of CK. In addition to the column address, AP is used to
invoke autoprecharge operation at the end of the burst read or write
cycle. If AP is HIGH, autoprecharge is selected and BA[12:0] defines
the bank to be precharged. If AP is LOW, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with
BA[12:0] to control which bank(s) to precharge. If AP is HIGH, all banks
will be precharged regardless of the state of BA[12:0] inputs. If AP is
LOW, then BA[12:0] are used to define which bank to precharge.
Not Connected
Note: 1-Rank, 2-Ranks module
221
S3
Address Signals
71
190
54
BA0
BA1
BA2
NC
188
183
63
182
61
60
180
58
179
177
70
57
176
196
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
A13
NC
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
NC
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
Address Signal 13
Not Connected
Note: Non CA parity modules based on 256 Mbit component
Rev. 1.22, 2007-06
07042006-834B-Z31V
7
QIMONDA [ QIMONDA AG ]
