TFP401, TFP401A
TI
PanelBus
DIGITAL RECEIVER
SLDS120B - MARCH 2000 – REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
PD
VIL
tpd(PDL)
PDO
VIL
tpd(PDOL)
PD
VIH
tp(PDH-V)
PD
Figure 9. Delay From PD Low to High Before
Inputs are Active
Figure 10. Minimum Time PD Low
TX2
50%
TX1
，
Figure 11. Analog Input Channel-to-Channel Skew
技
有
限
tt(HSC)
公
TX0
50%
司
18
圳
市
深
金
合
SCDT
Figure 12. Time Between DE Transitions to SCDT Low and SCDT High
讯
DE
科
tDEL
tDEH
DE
Figure 13. Minimum DE Low and Maximum DE High
10
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
66
tccs
43
41
5
tt(FSC)
85
，
QQ
DFO, ST, PIXS, STAG,
Rx(0-2)+, Rx(0-2)-,
OCK_INV
：
VIL
71
44
51
8
Figure 7. Delay From PD Low to Hi-Z Outputs
Figure 8. Delay From PDO Low to Hi-Z Outputs
twL(PDL_MIN)
19
QE(0-23), QO(0-23),
ODCK, DE, CTL(1-3),
HSYNC, VSYNC, SCDT
QE(0-23), QO(0-23),
ODCK, DE, CTL(2-3),
HSYNC, VSYNC
QUANTUM [ QUANTUM RESEARCH GROUP ]
