TFP401, TFP401A
TI
PanelBus
DIGITAL RECEIVER
SLDS120B - MARCH 2000 – REVISED JUNE 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
ac specifications
PARAMETER
VID(2)
tps
tccs
tijit
tf1
tr1
tr2
tf2
Differential input sensitivity†
Analog input intra-pair (+ to -) differen-
tial skew (see Note 6)
Analog Input inter-pair or channel-to-
channel skew (see Note 6)
Worse case differential input clock jitter
tolerance¶ (see Note 6)
Fall time of data and control signals#, ||
Rise time of data and control signals#, ||
Rise time of ODCK clock#
Fall time of ODCK clock#
ST = Low,
ST = High,
ST = Low,
ST = High,
ST = Low,
ST = High,
ST = Low,
ST = High,
CL=5 pF
CL=10 pF
CL=5 pF
CL=10 pF
CL=5 pF
CL=10 pF
CL=5 pF
CL=10 pF
TEST CONDITIONS
MIN
150
TYP
MAX
1560
0.4
UNIT
mVp-p
tbit‡
tpix§
ps
ns
ns
ns
ns
QQ
：
85
，
tsu1
Setup time, data and control signal to
falling edge of ODCK
2 pixel/clock, PIXS = high, STAG/ = high,
OCK_INV = low
2 pixel and STAG, PIXS = high,
STAG/ = low, OCK_INV = low
1 pixel/clock, PIXS = low, OCK_INV = low
43
41
5
1 pixel/clock, PIXS = low, OCK_INV = low
71
44
51
8
50
1.8
3.8
0.7
0.6
2.5
2.9
2.1
4
1.5
0.5
2.4
2.1
25
12.5
19
1
2.4
1.9
2.4
1.9
2.4
1.9
2.4
1.9
ns
公
司
tsu2
有
Setup time, data and control signal to
rising edge of ODCK
限
，
th1
Hold time, data and control signal to
falling edge of ODCK
2 pixel and STAG, PIXS = high,
STAG/ = low, OCK_INV = low
2 pixel/clock, PIXS = high,
STAG/ = high, OCK_INV = low
1 pixel/clock, PIXS = low, OCK_INV = high
2 pixel/clock, PIXS = high,
STAG/ = high, OCK_INV = high
2 pixel and STAG, PIXS = high,
STAG/ = low, OCK_INV = high
1 pixel/clock, PIXS = low, OCK_INV = high
2 pixel and STAG, PIXS = high,
STAG/ = low, OCK_INV = high
2 pixel/clock, PIXS = high,
STAG/ = high, OCK_INV = high
PIX = Low (1-PIX/CLK)
PIX = High (2-PIX/CLK)
18
66
ns
ns
th2
讯
Hold time, data and control signal to
rising edge of ODCK
科
技
ns
金
合
市
fODCK
ODCK frequency
165
82.5
MHz
ODCK duty-cycle
45%
60%
75%
† Specified as ac parameter to include sensitivity to overshoot, undershoot and reflection.
‡ tbit is 1/10 the pixel time, tpix
§ tpix is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to tpix in 1-pixel/clock mode or 2tpix when in
2-pixel/clock mode.
¶ Measured differentially at 50% crossing using ODCK output clock as trigger.
# Rise and fall times measured as time between 20% and 80% of signal amplitude.
|| Data and control signals are : QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[3:1]
k
Link active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity.
NOTE 6: By characterization
深
圳
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
7
QUANTUM [ QUANTUM RESEARCH GROUP ]
