TFP401, TFP401A
TI
PanelBus
DIGITAL RECEIVER
SLDS120B - MARCH 2000 – REVISED JUNE 2003
detailed description
fundamental operation
The TFP401/401A is a digital visual interface (DVI) compliant TMDS digital receiver that is used in digital flat
panel display systems to receive and decode TMDS encoded RGB pixel data streams. In a digital display
system a host, usually a PC or workstation, contains a TMDS compatible transmitter that receives 24 bit pixel
data along with appropriate control signals and encodes them into a high-speed low-voltage differential serial
bit stream fit for transmission over a twisted-pair cable to a display device. The display device, usually a
flat-panel monitor, will require a TMDS compatible receiver like the TI TFP401/401A to decode the serial bit
stream back to the same 24 bit pixel data and control signals that originated at the host. This decoded data can
then be applied directly to the flat panel drive circuitry to produce an image on the display. Since the host and
display can be separated by distances up to 5 meters or more, serial transmission of the pixel data is preferred.
To support modern display resolutions up to SXGA a high bandwidth receiver with good jitter and skew tolerance
is required.
司
Green[7:0]
Blue[7:0]
，
Red[7:0]
Channel – 2 (Rx2
±)
Channel – 1 (Rx1
±)
Channel – 0 (Rx0
±)
INPUT CHANNEL
Channel – 2 (Rx2
±)
Channel – 1 (Rx1
±)
Channel – 0 (Rx0
±)
18
RECEIVED PIXEL DATA
ACTIVE DISPLAY DE = HIGH
66
INPUT CHANNEL
CTL[1: 0] (see Note 6)
HSYNC, VSYNC
有
CTL[3:2]
限
RECEIVED CONTROL DATA
BLANKING DE = LOW
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技
深
圳
市
金
The TFP401/401A discriminates between valid pixel TMDS characters and control TMDS characters to
determine the state of active display versus blanking, i.e., state of DE.
合
讯
NOTE 7: Some TMDS transmitters transmit a CTL0 signal. The TFP401/401A decodes and
transfers CTL[3:1] and ignores CTL0 characters. CTL0 is not available as a
TFP401/401A output.
科
43
41
5
Three TMDS channels are used to receive RGB pixel data during active display time, DE = high. The same three
channels also receive control signals, HSYNC, VSYNC, and user defined control signals CTL[3:1]. These
control signals are received during inactive display or blanking-time. Blanking-time is when DE = low. The
following table maps the received input data to appropriate TMDS input channel in a DVI compliant system.
OUTPUT PINS
(VALID FOR DE = HIGH)
QE[23:16] QO[23:16]
QE[15:8] QO[15:8]
QE[7:0] QO[7:0]
OUTPUT PINS
(VALID FOR DE = LOW)
CTL[3:2]
CTL1
HSYNC, VSYNC
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
85
，
TMDS stands for transition minimized differential signaling. Only one of two possible TMDS characters for a
given pixel will be transmitted at a given time. The transmitter keeps a running count of the number of ones and
zeros previously sent and transmits the character that will minimize the number of transitions and approximate
a dc balance of the transmission line.
QQ
：
TMDS pixel data and control signal encoding
71
44
51
8
19
11
QUANTUM [ QUANTUM RESEARCH GROUP ]
