Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NL, M16C/6NN)
1. Overview
1.3 Block Diagram
Figure 1.1 shows a Block Diagram.
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7
Internal peripheral functions
Timer (16 bits)
Output (timer A): 5
Input (timer B): 6
Three-phase motor
control circuit
Watchdog timer
(15 bits)
A/D converter
(10 bits
✕
8 channels
Expandable up to 26 channels)
UART or
Clock synchronous serial I/O
(3 channels)
CRC calculation circuit (CCITT)
(Polynomial: X
16
+X
12
+X
5
+1)
System clock generation circuit
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
Clock synchronous serial I/O
(8 bits
✕
4 channels)
(4)
CAN module
(1 channel)
8
Port P8
Port P8_5
7
M16C/60 Series CPU core
R0H
R1H
R0L
R1L
R2
R3
A0
A1
FB
SB
USP
ISP
Memory
ROM
(1)
RAM
(2)
Port P9
DMAC
(2 channels)
8
INTB
Port P10
D/A converter
(8 bits
✕
2 channels)
PC
FLG
Multiplier
8
Port P14
(3)
Port P13
(3)
Port P12
(3)
Port P11
(3)
NOTES:
1: ROM size depends on MCU type.
2: RAM size depends on MCU type.
3: Ports P11 to P14 are only in the 128-pin version.
4: 8 bits
✕
2 channels in the 100-pin version.
2
8
8
8
Figure 1.1 Block Diagram
Rev.2.10 Aug 25, 2006
REJ03B0061-0210
page 4 of 67
RENESAS [ RENESAS TECHNOLOGY CORP ]
