X28HC256
CE Controlled Write Cycle
t
WC
ADDRESS
CE
t
t
AH
AS
t
CW
t
OES
OE
t
OEH
t
t
t
CS
CH
WE
DATA VALID
DATA IN
t
DS
DH
HIGH Z
DATA OUT
Page Write Cycle
OE
(NOTE 9)
CE
t
t
BLC
WP
WE
t
WPH
ADDRESS
(NOTE 10)
LAST BYTE
BYTE n + 2
I/O
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n + 1
t
WC
*For each successive write within the page write operation, A7 to A15 should be the same or
writes to an unknown address could occur.
NOTES:
9. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch
data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
10. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the
CE or WE controlled write cycle timing.
FN8108.2
May 7, 2007
14
ROCHESTER [ Rochester Electronics ]
