SA9401
A7
MRST
D0
D1
D2
V CC
D3
D4
D5
D6
D7
39 38
37 36 35 34 33 32
31 30 29
28
27
26
25
24
CLK_SEL
A0
A1
A2
A3
GND
A4
A5
A6
PCMFSC
CLKIN
40
41
42
43
44
1
2
3
4
5
6
SA9401
23
22
21
20
19
18
TEST
FS1
A8
A9
A11
GND
A10
A12
A13
PS2
WD_INT
7
8
9
10
11 12 13 14 15
16 17
DR-00603
Package : PLCC - 44
PIN DESCRIPTION
Pin No
1, 23
12, 34
27
6
8
10
5
11
13
15
41, 42, 43, 44,
2, 3, 4, 39, 26,
25, 22, 24,
21, 20
I/0
I
I
I
I
O
O
O
O
O
O
O
Designation
GND
VCC
FS1
CLKIN
2MCLK
8KFS
PCMFSC
INTRFRQ
INTRCAD
PCM_OUT
A0..A13
2
sames
CLKDIV2
2MCLK
PS0
8KFS
INTRFRQ
VCC
INTRCAD
PS1
PCM_OUT
WD_RST
WD_EN
Description
Supply Ground
+5V Power Supply
Frame Synchronisation (active low)
Master clock input (either 8192kHz or 2048 Khz
dependent on logic level of "CLK _SEL")
2048 kHz clock derived internally from CLKIN
8 kHz Frame Synchronisation output.
8 kHz Auxilliary Frame Synchronisation Output
Square Wave Intrude Tone
Intrude Tone Cadence Signal
Tri-state PCM Highway tone output
EPROM Address Lines
SAMES [ SAMES ]
