K4D263238F
128M DDR SDRAM
1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
FEATURES
• 2.5V ± 5% power supply for device operation
• 2.5V ± 5% power supply for I/O interface
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 3 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
• Full page burst length for sequential burst type only
• Start address of the full page burst should be even
• All inputs except data & DM are sampled at the positive
going edge of the system clock
• Differential clock input
• No Write Interrupted by Read function
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 32ms refresh period (4K cycle)
• 100pin TQFP package
• Maximum clock frequency up to 250MHz
• Maximum data rate up to 500Mbps/pin
ORDERING INFORMATION
Part NO.
K4D263238F-QC40
K4D263238F-QC50
Max Freq.
250MHz
200MHz
Max Data Rate
500Mbps/pin
400Mbps/pin
Interface
SSTL_2
Package
100 TQFP
K4D263238F-UC is the Lead Free package part number.
GENERAL DESCRIPTION
FOR 1M x 32Bit x 4 Bank DDR SDRAM
The K4D263238F is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 1,048,576 words by
32 bits, fabricated with SAMSUNG
′
s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to
2.0GB/s/chip.
I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
- 3 -
Rev 1.1 (May 2003)
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
