K4J55323QG
256M GDDR3 SDRAM
2M x 32Bit x 4 Banks Graphic Double Data Rate 3 Synchronous DRAM
with Uni-directional Data Strobe
1.0 FEATURES
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1.8V + 0.1V power supply for device operation
1.8V + 0.1V power supply for I/O interface
On-Die Termination (ODT)
Output Driver Strength adjustment by EMRS
Calibrated output drive
1.8V Pseudo Open drain compatible inputs/outputs
4 internal banks for concurrent operation
Differential clock inputs (CK and CK)
Commands entered on each positive CK edge
CAS latency : 4, 5, 6, 7, 8, 9, 10, 11 (clock)
Additive latency (AL): 0 and 1 (clock)
Programmable Burst length : 4 and 8
Programmable Write latency : 1, 2, 3, 4, 5, 6 and 7 (clock)
Single ended READ strobe (RDQS) per byte
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Single ended WRITE strobe (WDQS) per byte
RDQS edge-aligned with data for READs
WDQS center-aligned with data for WRITEs
Data Mask(DM) for masking WRITE data
Auto & Self refresh modes
Auto Precharge option
32ms, auto refresh (4K cycle)
136 Ball FBGA
Maximum clock frequency up to 800MHz
Maximum data rate up to 1.6Gbps/pin
DLL for outputs
Boundary scan function with SEN pin
Mirror function with MF pin
2.0 ORDERING INFORMATION
Part Number
K4J55323QG-BC12
K4J55323QG-BC14
K4J55323QG-BC16
K4J55323QG-BC20
Max Freq.
800MHz
700MHz
600MHz
500MHz
Max Data Rate
1.6Gbps/pin
1.4Gbps/pin
1.2Gbps/pin
1.0Gbps/pin
Pseudo
Open Drain_18
136 Ball FBGA
Interface
Package
K4J55323QC-AC** is leaded package part number
3.0 GENERAL DESCRIPTION
FOR 2M x 32Bit x 4 Bank GDDR3 SDRAM
The K4J55323QG is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits, fab-
ricated with SAMSUNG
’s
high performance CMOS technology. Synchronous features with Data Strobe allow extremely high perfor-
mance up to 6.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, and
programmable latencies allow the device to be useful for a variety of high performance memory system applications.
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Rev. 1.1 November 2005
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
