K4J55323QG
7.3 MODE REGISTER SET(MRS)
256M GDDR3 SDRAM
The mode register stores the data for controlling the various operating modes of GDDR3 SDRAM. It programs CAS latency, address-
ing mode, test mode and various vendor specific options to make GDDR3 SDRAM useful for variety of different applications. The
default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for the proper opera-
tion. The mode register is written by asserting low on CS, RAS, CAS and WE (The GDDR3 SDRAM should be in active mode with CKE
already high prior to writing into the mode register). The state of address pins A
0
~ A
11
and BA
0
, BA
1
in the same cycle as CS, RAS,
CAS and WE going low is written in the mode register. Minimum clock cycles specified as tMRD are required to complete the write oper-
ation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during
operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The Burst
length uses A
0
~ A
1
. CAS latency (read latency from column address) uses A
2
, A
6
~ A
4
. A
7
is used for test mode. A
8
is used for DLL
reset. A
9
~ A
11
are used for Write latency. Refer to the table for specific codes for various addressing modes and CAS latencies.
BA
1
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
0
0
WL
DLL
TM
CAS Latency
BT
CL
Burst Length
Test Mode
BA
1
0
0
BA
0
0
1
A
n
~ A
0
MRS
EMRS
A
7
0
1
mode
Normal
Test
Burst Type
A
3
0
1
Burst Type
Sequential
Reserved
DLL
A
8
DLL Reset
No
Yes
0
Write Latency
Reserved
1
2
3
4
5
6
7
1
Write Latency
A
11
0
0
0
0
1
1
1
1
A
10
0
0
1
1
0
0
1
1
A
9
0
1
0
1
0
1
0
1
Note : DLL reset is self-clearing
Burst Length
CAS Latency
A
2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A
6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A
5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CAS Latency
8
9
10
11
4
5
6
7
Reserved(12)
Reserved(13)
Reserved(14)
Reserved(15)
Reserved
Reserved
Reserved
Reserved
A
1
0
0
1
1
A
0
0
1
0
1
Burst Length
Reserved
Reserved
4
8
RFU(Reserved for future use) should
stay "0" during MRS cycle
9 of 53
Rev. 1.1 November 2005
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
