K6R1004V1D
WRITE CYCLE*
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End of Write to Output Low-Z
Symbol
t
WC
t
CW
t
AS
t
AW
t
WP
t
WP1
t
WR
t
WHZ
t
DW
t
DH
t
OW
K6R1004V1D-08
PRELIMINARY
PRELIMINARY
for AT&T
CMOS SRAM
K6R1004V1D-10
Min
8
6
0
6
6
8
0
0
4
0
3
Max
-
-
-
-
-
-
-
4
-
-
-
Min
10
7
0
7
7
10
0
0
5
0
3
Max
-
-
-
-
-
-
-
5
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* The above parameters are also guaranteed at industrial temperature range.
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
)
t
RC
Address
t
OH
Data Out
Previous Valid Data
t
AA
Valid Data
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
t
RC
Address
t
AA
t
CO
t
HZ(3,4,5)
CS
t
OHZ
OE
t
OLZ
Data out
I
CC
I
SB
High-Z
t
OE
t
DH
Valid Data
t
PD
50%
50%
t
LZ(4,5)
t
PU
V
CC
Current
-6-
Rev. 3.0
July 2004
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
