K6R1004V1D
NOTES(READ
CYCLE)
PRELIMINARY
PRELIMINARY
for AT&T
CMOS SRAM
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
OH
or
V
OL
levels.
4. At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device and from device to
device.
5. Transition is measured
±200mV
from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=V
IL.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1)
(OE= Clock)
t
WC
Address
t
AW
OE
t
CW(3)
CS
t
AS(4)
WE
t
DW
Data in
High-Z
t
OHZ(6)
Data out
High-Z(8)
Valid Data
t
DH
t
WP(2)
t
WR(5)
TIMING WAVEFORM OF WRITE CYCLE(2)
(OE=Low Fixed)
t
WC
Address
t
AW
CS
t
AS(4)
WE
t
DW
Data in
High-Z
t
WHZ(6)
Data out
High-Z(8)
Valid Data
t
OW
(10)
(9)
t
CW(3)
t
WP1(2)
t
WR(5)
t
DH
-7-
Rev. 3.0
July 2004
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
