KM68512A Family
TIMING WAVEFORM OF WRITE CYCLE(3)
(CS
2
Controlled)
CMOS SRAM
t
WC
Address
t
AS(3)
CS
1
t
AW
CS
2
t
CW(2)
t
WP(1)
t
DW
Data in
Data Valid
t
DH
t
CW(2)
t
WR(4)
WE
Data out
NOTES
(WRITE CYCLE)
High-Z
High-Z
1. A write occurs during the overlap of a low CS
1
, a high CS
2
and a low WE. A write begins at the latest transition among CS
1
goes low,
CS
2
going high and WE going low : A write end at the earliest transition among CS
1
going high, CS
2
going low and WE going high,
t
WP
is measured from the begining of write to the end of write.
2. t
CW
is measured from the CS
1
going low or CS
2
going high to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR(1)
applied in case a write ends as CS
1
or WE going high t
WR(2)
applied in case a write ends as CS
2
going to low.
DATA RETENTION WAVE FORM
CS
1
controlled
V
CC
4.5V
t
SDR
Data Retention Mode
t
RDR
2.2V
V
DR
CS1≥V
CC
- 0.2V
CS
1
GND
CS
2
controlled
V
CC
4.5V
CS
2
t
SDR
Data Retention Mode
t
RDR
V
DR
0.4V
GND
CS
2
≤0.2V
8
Revision 4.0
January 1997
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
